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[/] - Rev 59

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Rev	Log message	Author	Age	Path
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4105d 05h	/
58	made fifo full a warning	JonasDC	4108d 05h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4108d 05h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4108d 08h	/
55	updated resource usage in comments	JonasDC	4109d 04h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4109d 04h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4109d 11h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4109d 11h	/
51	true dual port ram for xilinx	JonasDC	4109d 12h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4109d 12h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4121d 07h	/
48	Tag of the starting version of the project	JonasDC	4121d 07h	/
47	added documentation for the IP core.	JonasDC	4189d 12h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4189d 12h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4189d 12h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4193d 06h	/
43	made the core parameters generics	JonasDC	4193d 06h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4199d 13h	/
41	removed deprecated files from version control	JonasDC	4199d 13h	/
40	adjusted core instantiation to new core module name	JonasDC	4207d 17h	/

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[/] - Rev 59

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