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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
62	not used anymore	JonasDC	4076d 19h	/
61	updated comments, added optional altera constraint	JonasDC	4076d 19h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4079d 09h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4079d 10h	/
58	made fifo full a warning	JonasDC	4082d 10h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4082d 10h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4082d 13h	/
55	updated resource usage in comments	JonasDC	4083d 09h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4083d 10h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4083d 16h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4083d 17h	/
51	true dual port ram for xilinx	JonasDC	4083d 17h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4083d 17h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4095d 12h	/
48	Tag of the starting version of the project	JonasDC	4095d 12h	/
47	added documentation for the IP core.	JonasDC	4163d 17h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 17h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 17h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4167d 11h	/
43	made the core parameters generics	JonasDC	4167d 11h	/

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Subversion Repositories mod_sim_exp

[/] - Rev 62

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