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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
64	added synthesis reports of xilinx and altera	JonasDC	4077d 05h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4077d 05h	/
62	not used anymore	JonasDC	4077d 08h	/
61	updated comments, added optional altera constraint	JonasDC	4077d 08h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4079d 22h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4079d 23h	/
58	made fifo full a warning	JonasDC	4082d 23h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4082d 23h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4083d 01h	/
55	updated resource usage in comments	JonasDC	4083d 22h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4083d 22h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4084d 05h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4084d 05h	/
51	true dual port ram for xilinx	JonasDC	4084d 06h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4084d 06h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4096d 01h	/
48	Tag of the starting version of the project	JonasDC	4096d 01h	/
47	added documentation for the IP core.	JonasDC	4164d 06h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4164d 06h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4164d 06h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4167d 23h	/
43	made the core parameters generics	JonasDC	4167d 23h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4174d 07h	/
41	removed deprecated files from version control	JonasDC	4174d 07h	/
40	adjusted core instantiation to new core module name	JonasDC	4182d 11h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4182d 22h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4183d 04h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4187d 01h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4187d 21h	/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4188d 00h	/

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