URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 65

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4078d 08h	/
64	added synthesis reports of xilinx and altera	JonasDC	4078d 14h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4078d 14h	/
62	not used anymore	JonasDC	4078d 16h	/
61	updated comments, added optional altera constraint	JonasDC	4078d 16h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4081d 07h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4081d 07h	/
58	made fifo full a warning	JonasDC	4084d 07h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4084d 07h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4084d 10h	/
55	updated resource usage in comments	JonasDC	4085d 07h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4085d 07h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4085d 13h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4085d 14h	/
51	true dual port ram for xilinx	JonasDC	4085d 15h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4085d 15h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4097d 10h	/
48	Tag of the starting version of the project	JonasDC	4097d 10h	/
47	added documentation for the IP core.	JonasDC	4165d 14h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4165d 14h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4165d 14h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4169d 08h	/
43	made the core parameters generics	JonasDC	4169d 08h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4175d 16h	/
41	removed deprecated files from version control	JonasDC	4175d 16h	/
40	adjusted core instantiation to new core module name	JonasDC	4183d 20h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4184d 07h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4184d 13h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4188d 10h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4189d 06h	/

Browse

Tools

Subversion Repositories mod_sim_exp

[/] - Rev 65

Filtering Options