URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 67

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4083d 13h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4083d 14h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4091d 05h	/
64	added synthesis reports of xilinx and altera	JonasDC	4091d 11h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4091d 11h	/
62	not used anymore	JonasDC	4091d 14h	/
61	updated comments, added optional altera constraint	JonasDC	4091d 14h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4094d 04h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4094d 04h	/
58	made fifo full a warning	JonasDC	4097d 05h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4097d 05h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4097d 07h	/
55	updated resource usage in comments	JonasDC	4098d 04h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4098d 04h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4098d 11h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4098d 11h	/
51	true dual port ram for xilinx	JonasDC	4098d 12h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4098d 12h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4110d 07h	/
48	Tag of the starting version of the project	JonasDC	4110d 07h	/
47	added documentation for the IP core.	JonasDC	4178d 12h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4178d 12h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4178d 12h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4182d 05h	/
43	made the core parameters generics	JonasDC	4182d 05h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4188d 13h	/
41	removed deprecated files from version control	JonasDC	4188d 13h	/
40	adjusted core instantiation to new core module name	JonasDC	4196d 17h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4197d 04h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4197d 10h	/

Browse

Tools

Subversion Repositories mod_sim_exp

[/] - Rev 67

Filtering Options