OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 73

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 updated plb interface, mem_style and device generics added JonasDC 4290d 12h /
72 deleted old resources JonasDC 4291d 12h /
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4291d 12h /
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4291d 12h /
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4291d 12h /
68 branch no longer needed JonasDC 4291d 14h /
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4291d 15h /
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4291d 15h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4299d 07h /
64 added synthesis reports of xilinx and altera JonasDC 4299d 12h /
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4299d 13h /
62 not used anymore JonasDC 4299d 15h /
61 updated comments, added optional altera constraint JonasDC 4299d 15h /
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4302d 06h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4302d 06h /
58 made fifo full a warning JonasDC 4305d 06h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4305d 06h /
56 this is a branch to test performance of a new style of ram JonasDC 4305d 09h /
55 updated resource usage in comments JonasDC 4306d 05h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4306d 06h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.