URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 73

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Rev	Log message	Author	Age	Path
73	updated plb interface, mem_style and device generics added	JonasDC	4078d 04h	/
72	deleted old resources	JonasDC	4079d 04h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4079d 04h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4079d 04h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4079d 04h	/
68	branch no longer needed	JonasDC	4079d 06h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4079d 07h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4079d 07h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4086d 23h	/
64	added synthesis reports of xilinx and altera	JonasDC	4087d 05h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4087d 05h	/
62	not used anymore	JonasDC	4087d 07h	/
61	updated comments, added optional altera constraint	JonasDC	4087d 07h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4089d 22h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4089d 22h	/
58	made fifo full a warning	JonasDC	4092d 22h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4092d 22h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4093d 01h	/
55	updated resource usage in comments	JonasDC	4093d 22h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4093d 22h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4094d 04h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4094d 05h	/
51	true dual port ram for xilinx	JonasDC	4094d 06h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4094d 06h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4106d 01h	/
48	Tag of the starting version of the project	JonasDC	4106d 01h	/
47	added documentation for the IP core.	JonasDC	4174d 05h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4174d 05h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4174d 05h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4177d 23h	/

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Subversion Repositories mod_sim_exp

[/] - Rev 73

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