URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 73

Rev	Log message	Author	Age	Path
53	correctly inferred ram for altera dual port ram	JonasDC	4093d 23h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4094d 00h	/
51	true dual port ram for xilinx	JonasDC	4094d 00h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4094d 00h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4105d 19h	/
48	Tag of the starting version of the project	JonasDC	4105d 20h	/
47	added documentation for the IP core.	JonasDC	4174d 00h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4174d 00h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4174d 00h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4177d 18h	/