URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 76

Rev	Log message	Author	Age	Path
56	this is a branch to test performance of a new style of ram	JonasDC	4083d 15h	/
55	updated resource usage in comments	JonasDC	4084d 11h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4084d 11h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4084d 18h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4084d 18h	/
51	true dual port ram for xilinx	JonasDC	4084d 19h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4084d 19h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4096d 14h	/
48	Tag of the starting version of the project	JonasDC	4096d 14h	/
47	added documentation for the IP core.	JonasDC	4164d 19h	/