OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 84

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4022d 12h /
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4024d 13h /
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4041d 09h /
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4041d 09h /
80 renamed to version 1.1 to follow the versioning system JonasDC 4051d 03h /
79 Tag for version 1.3 (with new ram style JonasDC 4051d 03h /
78 updated documentation with new RAM style information JonasDC 4051d 03h /
77 found fault in code, now synthesizes normally JonasDC 4057d 00h /
76 testbench update JonasDC 4059d 11h /
75 made rw_address a vector of a fixed width JonasDC 4059d 11h /
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4062d 07h /
73 updated plb interface, mem_style and device generics added JonasDC 4063d 07h /
72 deleted old resources JonasDC 4064d 07h /
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4064d 07h /
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4064d 07h /
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4064d 07h /
68 branch no longer needed JonasDC 4064d 09h /
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4064d 10h /
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4064d 10h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4072d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.