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Rev	Log message	Author	Age	Path
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4025d 20h	/
86	update on previous	JonasDC	4025d 20h	/
85	changed so that reset now also affects slave register	JonasDC	4025d 20h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4027d 05h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4029d 06h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4046d 02h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4046d 02h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4055d 20h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4055d 20h	/
78	updated documentation with new RAM style information	JonasDC	4055d 20h	/
77	found fault in code, now synthesizes normally	JonasDC	4061d 17h	/
76	testbench update	JonasDC	4064d 04h	/
75	made rw_address a vector of a fixed width	JonasDC	4064d 04h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4067d 00h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4067d 23h	/
72	deleted old resources	JonasDC	4068d 23h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4068d 23h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4069d 00h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4069d 00h	/
68	branch no longer needed	JonasDC	4069d 02h	/

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[/] - Rev 87

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