| Rev |
Log message |
Author |
Age |
Path |
| 94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3956d 18h |
/ |
| 93 |
Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. |
JonasDC |
3958d 23h |
/ |
| 92 |
updated documentation with minor interrupt changes of AXI interface |
JonasDC |
3958d 23h |
/ |
| 91 |
changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. |
JonasDC |
3961d 02h |
/ |
| 90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3962d 17h |
/ |
| 89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4026d 15h |
/ |
| 88 |
small update on documentation, changed fault in axi control_reg |
JonasDC |
4032d 16h |
/ |
| 87 |
updated documentation to version 1.4
core now supports the AXI4-Lite bus |
JonasDC |
4032d 17h |
/ |
| 86 |
update on previous |
JonasDC |
4032d 17h |
/ |
| 85 |
changed so that reset now also affects slave register |
JonasDC |
4032d 17h |
/ |
| 84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4034d 01h |
/ |
| 83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4036d 02h |
/ |
| 82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4052d 22h |
/ |
| 81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4052d 22h |
/ |
| 80 |
renamed to version 1.1 to follow the versioning system |
JonasDC |
4062d 16h |
/ |
| 79 |
Tag for version 1.3 (with new ram style |
JonasDC |
4062d 16h |
/ |
| 78 |
updated documentation with new RAM style information |
JonasDC |
4062d 16h |
/ |
| 77 |
found fault in code, now synthesizes normally |
JonasDC |
4068d 14h |
/ |
| 76 |
testbench update |
JonasDC |
4071d 01h |
/ |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4071d 01h |
/ |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4073d 21h |
/ |
| 73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4074d 20h |
/ |
| 72 |
deleted old resources |
JonasDC |
4075d 20h |
/ |
| 71 |
added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM |
JonasDC |
4075d 20h |
/ |
| 70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4075d 20h |
/ |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4075d 20h |
/ |
| 68 |
branch no longer needed |
JonasDC |
4075d 22h |
/ |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4075d 23h |
/ |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4076d 00h |
/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4083d 15h |
/ |
