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Rev Log message Author Age Path
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3556d 05h /
73 updated plb interface, mem_style and device generics added JonasDC 3557d 04h /
72 deleted old resources JonasDC 3558d 04h /
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 3558d 04h /
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3558d 05h /
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3558d 05h /
68 branch no longer needed JonasDC 3558d 07h /
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 3558d 08h /
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 3558d 08h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3566d 00h /

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