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Rev Log message Author Age Path
77 found fault in code, now synthesizes normally JonasDC 3557d 19h /
76 testbench update JonasDC 3560d 06h /
75 made rw_address a vector of a fixed width JonasDC 3560d 06h /
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3563d 02h /
73 updated plb interface, mem_style and device generics added JonasDC 3564d 01h /
72 deleted old resources JonasDC 3565d 01h /
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 3565d 01h /
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3565d 01h /
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3565d 01h /
68 branch no longer needed JonasDC 3565d 03h /

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