Rev |
Log message |
Author |
Age |
Path |
104 |
Release of version 1.5, this version supports an independent clock for the multiplier |
JonasDC |
3907d 13h |
/mod_sim_exp |
103 |
Updated documentation to version 1.5 with dual-clock support |
JonasDC |
3907d 13h |
/mod_sim_exp |
102 |
Added some extra information for the test generation software |
JonasDC |
3907d 13h |
/mod_sim_exp |
101 |
added README file for simulation, minor update for Makefile clean target. |
JonasDC |
3907d 17h |
/mod_sim_exp |
100 |
added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated |
JonasDC |
3926d 00h |
/mod_sim_exp |
99 |
removed tag, wrong directory tagged |
JonasDC |
3926d 00h |
/mod_sim_exp |
98 |
added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. |
JonasDC |
3926d 00h |
/mod_sim_exp |
97 |
changes in makefile, and fifo's are now also in mod_sim_exp library |
JonasDC |
3942d 18h |
/mod_sim_exp |
96 |
minor makefile update |
JonasDC |
3943d 18h |
/mod_sim_exp |
95 |
new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination. |
JonasDC |
3943d 18h |
/mod_sim_exp |
94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3956d 14h |
/mod_sim_exp |
93 |
Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. |
JonasDC |
3958d 19h |
/mod_sim_exp |
92 |
updated documentation with minor interrupt changes of AXI interface |
JonasDC |
3958d 19h |
/mod_sim_exp |
91 |
changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. |
JonasDC |
3960d 22h |
/mod_sim_exp |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3962d 13h |
/mod_sim_exp |
89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4026d 11h |
/mod_sim_exp |
88 |
small update on documentation, changed fault in axi control_reg |
JonasDC |
4032d 12h |
/mod_sim_exp |
87 |
updated documentation to version 1.4
core now supports the AXI4-Lite bus |
JonasDC |
4032d 12h |
/mod_sim_exp |
86 |
update on previous |
JonasDC |
4032d 13h |
/mod_sim_exp |
85 |
changed so that reset now also affects slave register |
JonasDC |
4032d 13h |
/mod_sim_exp |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4033d 21h |
/mod_sim_exp |
83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4035d 22h |
/mod_sim_exp |
82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4052d 18h |
/mod_sim_exp |
81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4052d 18h |
/mod_sim_exp |
80 |
renamed to version 1.1 to follow the versioning system |
JonasDC |
4062d 12h |
/mod_sim_exp |
79 |
Tag for version 1.3 (with new ram style |
JonasDC |
4062d 12h |
/mod_sim_exp |
78 |
updated documentation with new RAM style information |
JonasDC |
4062d 12h |
/mod_sim_exp |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4068d 09h |
/mod_sim_exp |
76 |
testbench update |
JonasDC |
4070d 20h |
/mod_sim_exp |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4070d 20h |
/mod_sim_exp |