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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 13

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Rev	Log message	Author	Age	Path
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4202d 19h	/mod_sim_exp/
12	updated comments, file is now completely according to design rules	JonasDC	4202d 19h	/mod_sim_exp/
11	simulation output folder	JonasDC	4202d 21h	/mod_sim_exp/
10	changed signal input port names to correct name	JonasDC	4203d 00h	/mod_sim_exp/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4203d 00h	/mod_sim_exp/
8	added descriptive comments	JonasDC	4203d 02h	/mod_sim_exp/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 03h	/mod_sim_exp/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 03h	/mod_sim_exp/
5	not needed on svn, is generated by testbench	JonasDC	4203d 03h	/mod_sim_exp/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 05h	/mod_sim_exp/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4203d 19h	/mod_sim_exp/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4208d 01h	/mod_sim_exp/
1	The project and the structure was created	root	4210d 00h	/mod_sim_exp/

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