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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 29

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Rev Log message Author Age Path
29 added software for generation of test input for the tesbenches JonasDC 4280d 07h /mod_sim_exp/
28 updated makefile for new pipeline sources JonasDC 4280d 07h /mod_sim_exp/
27 test input values for multiplier_tb JonasDC 4280d 07h /mod_sim_exp/
26 testbench for only the montgommery multiplier JonasDC 4280d 07h /mod_sim_exp/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4280d 07h /mod_sim_exp/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4283d 16h /mod_sim_exp/
23 added descriptive comments JonasDC 4283d 17h /mod_sim_exp/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4286d 11h /mod_sim_exp/
21 changed x_i signal to xi JonasDC 4287d 19h /mod_sim_exp/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4287d 19h /mod_sim_exp/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4292d 14h /mod_sim_exp/
18 updated stages with comments and renamed some signals for consistency JonasDC 4293d 14h /mod_sim_exp/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4293d 19h /mod_sim_exp/
16 package with modified generic parameter for register_n JonasDC 4294d 08h /mod_sim_exp/
15 changed generic for register width from n to width for consistency JonasDC 4294d 08h /mod_sim_exp/
14 changed comments, file is now according to OC design rules JonasDC 4294d 08h /mod_sim_exp/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4294d 08h /mod_sim_exp/
12 updated comments, file is now completely according to design rules JonasDC 4294d 08h /mod_sim_exp/
11 simulation output folder JonasDC 4294d 11h /mod_sim_exp/
10 changed signal input port names to correct name JonasDC 4294d 13h /mod_sim_exp/

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