Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 37


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17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 3812d 03h /mod_sim_exp/
16 package with modified generic parameter for register_n JonasDC 3812d 16h /mod_sim_exp/
15 changed generic for register width from n to width for consistency JonasDC 3812d 16h /mod_sim_exp/
14 changed comments, file is now according to OC design rules JonasDC 3812d 17h /mod_sim_exp/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 3812d 17h /mod_sim_exp/
12 updated comments, file is now completely according to design rules JonasDC 3812d 17h /mod_sim_exp/
11 simulation output folder JonasDC 3812d 19h /mod_sim_exp/
10 changed signal input port names to correct name JonasDC 3812d 22h /mod_sim_exp/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 3812d 22h /mod_sim_exp/
8 added descriptive comments JonasDC 3813d 00h /mod_sim_exp/

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