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[/] [mod_sim_exp/] - Rev 38

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Rev	Log message	Author	Age	Path
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4182d 13h	/mod_sim_exp/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4186d 10h	/mod_sim_exp/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4187d 06h	/mod_sim_exp/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4187d 08h	/mod_sim_exp/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4187d 09h	/mod_sim_exp/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4187d 12h	/mod_sim_exp/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4187d 13h	/mod_sim_exp/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4187d 18h	/mod_sim_exp/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4187d 19h	/mod_sim_exp/
29	added software for generation of test input for the tesbenches	JonasDC	4188d 08h	/mod_sim_exp/
28	updated makefile for new pipeline sources	JonasDC	4188d 09h	/mod_sim_exp/
27	test input values for multiplier_tb	JonasDC	4188d 09h	/mod_sim_exp/
26	testbench for only the montgommery multiplier	JonasDC	4188d 09h	/mod_sim_exp/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4188d 09h	/mod_sim_exp/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4191d 18h	/mod_sim_exp/
23	added descriptive comments	JonasDC	4191d 19h	/mod_sim_exp/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4194d 12h	/mod_sim_exp/
21	changed x_i signal to xi	JonasDC	4195d 20h	/mod_sim_exp/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4195d 20h	/mod_sim_exp/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4200d 15h	/mod_sim_exp/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 38

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