| Rev |
Log message |
Author |
Age |
Path |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4193d 09h |
/mod_sim_exp/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4197d 06h |
/mod_sim_exp/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4198d 02h |
/mod_sim_exp/ |
| 35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4198d 05h |
/mod_sim_exp/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4198d 06h |
/mod_sim_exp/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4198d 09h |
/mod_sim_exp/ |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4198d 10h |
/mod_sim_exp/ |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4198d 15h |
/mod_sim_exp/ |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4198d 15h |
/mod_sim_exp/ |
| 29 |
added software for generation of test input for the tesbenches |
JonasDC |
4199d 04h |
/mod_sim_exp/ |
| 28 |
updated makefile for new pipeline sources |
JonasDC |
4199d 05h |
/mod_sim_exp/ |
| 27 |
test input values for multiplier_tb |
JonasDC |
4199d 05h |
/mod_sim_exp/ |
| 26 |
testbench for only the montgommery multiplier |
JonasDC |
4199d 05h |
/mod_sim_exp/ |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4199d 05h |
/mod_sim_exp/ |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4202d 14h |
/mod_sim_exp/ |
| 23 |
added descriptive comments |
JonasDC |
4202d 15h |
/mod_sim_exp/ |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4205d 09h |
/mod_sim_exp/ |
| 21 |
changed x_i signal to xi |
JonasDC |
4206d 16h |
/mod_sim_exp/ |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4206d 17h |
/mod_sim_exp/ |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4211d 12h |
/mod_sim_exp/ |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4212d 11h |
/mod_sim_exp/ |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4212d 16h |
/mod_sim_exp/ |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4213d 05h |
/mod_sim_exp/ |
| 15 |
changed generic for register width from n to width for consistency |
JonasDC |
4213d 06h |
/mod_sim_exp/ |
| 14 |
changed comments, file is now according to OC design rules |
JonasDC |
4213d 06h |
/mod_sim_exp/ |
| 13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4213d 06h |
/mod_sim_exp/ |
| 12 |
updated comments, file is now completely according to design rules |
JonasDC |
4213d 06h |
/mod_sim_exp/ |
| 11 |
simulation output folder |
JonasDC |
4213d 08h |
/mod_sim_exp/ |
| 10 |
changed signal input port names to correct name |
JonasDC |
4213d 11h |
/mod_sim_exp/ |
| 9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4213d 11h |
/mod_sim_exp/ |
