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[/] [mod_sim_exp/] - Rev 39

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Rev Log message Author Age Path
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4235d 06h /mod_sim_exp/
18 updated stages with comments and renamed some signals for consistency JonasDC 4236d 05h /mod_sim_exp/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4236d 10h /mod_sim_exp/
16 package with modified generic parameter for register_n JonasDC 4236d 23h /mod_sim_exp/
15 changed generic for register width from n to width for consistency JonasDC 4236d 23h /mod_sim_exp/
14 changed comments, file is now according to OC design rules JonasDC 4237d 00h /mod_sim_exp/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4237d 00h /mod_sim_exp/
12 updated comments, file is now completely according to design rules JonasDC 4237d 00h /mod_sim_exp/
11 simulation output folder JonasDC 4237d 02h /mod_sim_exp/
10 changed signal input port names to correct name JonasDC 4237d 05h /mod_sim_exp/

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