URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 44

Rev	Log message	Author	Age	Path
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4227d 02h	/mod_sim_exp
23	added descriptive comments	JonasDC	4227d 03h	/mod_sim_exp
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4229d 20h	/mod_sim_exp
21	changed x_i signal to xi	JonasDC	4231d 04h	/mod_sim_exp
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4231d 04h	/mod_sim_exp
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4235d 23h	/mod_sim_exp
18	updated stages with comments and renamed some signals for consistency	JonasDC	4236d 23h	/mod_sim_exp
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4237d 04h	/mod_sim_exp
16	package with modified generic parameter for register_n	JonasDC	4237d 17h	/mod_sim_exp
15	changed generic for register width from n to width for consistency	JonasDC	4237d 17h	/mod_sim_exp