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[/] [mod_sim_exp/] - Rev 47

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Rev Log message Author Age Path
47 added documentation for the IP core. JonasDC 3592d 21h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3592d 21h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3592d 21h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3596d 14h /mod_sim_exp/
43 made the core parameters generics JonasDC 3596d 14h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3602d 22h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 3602d 22h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 3611d 02h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3611d 13h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3611d 19h /mod_sim_exp/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3615d 16h /mod_sim_exp/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 3616d 12h /mod_sim_exp/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3616d 15h /mod_sim_exp/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 3616d 16h /mod_sim_exp/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 3616d 18h /mod_sim_exp/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 3616d 19h /mod_sim_exp/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3617d 01h /mod_sim_exp/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3617d 01h /mod_sim_exp/
29 added software for generation of test input for the tesbenches JonasDC 3617d 14h /mod_sim_exp/
28 updated makefile for new pipeline sources JonasDC 3617d 15h /mod_sim_exp/

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