OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 50

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3577d 14h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3589d 09h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 3589d 09h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 3657d 14h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3657d 14h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3657d 14h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3661d 08h /mod_sim_exp/
43 made the core parameters generics JonasDC 3661d 08h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3667d 15h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 3667d 16h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 3675d 20h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3676d 07h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3676d 12h /mod_sim_exp/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3680d 09h /mod_sim_exp/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 3681d 05h /mod_sim_exp/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3681d 08h /mod_sim_exp/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 3681d 09h /mod_sim_exp/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 3681d 12h /mod_sim_exp/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 3681d 13h /mod_sim_exp/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3681d 18h /mod_sim_exp/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.