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[/] [mod_sim_exp/] - Rev 55

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Rev Log message Author Age Path
55 updated resource usage in comments JonasDC 3574d 18h /mod_sim_exp/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3574d 18h /mod_sim_exp/
53 correctly inferred ram for altera dual port ram JonasDC 3575d 01h /mod_sim_exp/
52 correct inferring of blockram, no additional resources. JonasDC 3575d 01h /mod_sim_exp/
51 true dual port ram for xilinx JonasDC 3575d 02h /mod_sim_exp/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3575d 02h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3586d 21h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 3586d 21h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 3655d 02h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3655d 02h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3655d 02h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3658d 19h /mod_sim_exp/
43 made the core parameters generics JonasDC 3658d 19h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3665d 03h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 3665d 03h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 3673d 07h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3673d 18h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3674d 00h /mod_sim_exp/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3677d 21h /mod_sim_exp/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 3678d 17h /mod_sim_exp/

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