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[/] [mod_sim_exp/] - Rev 6

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6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3697d 23h /mod_sim_exp/
5 not needed on svn, is generated by testbench JonasDC 3697d 23h /mod_sim_exp/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3698d 00h /mod_sim_exp/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3698d 14h /mod_sim_exp/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3702d 20h /mod_sim_exp/
1 The project and the structure was created root 3704d 20h /mod_sim_exp/

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