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[/] [mod_sim_exp/] - Rev 62

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Rev Log message Author Age Path
62 not used anymore JonasDC 3564d 01h /mod_sim_exp/
61 updated comments, added optional altera constraint JonasDC 3564d 01h /mod_sim_exp/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3566d 15h /mod_sim_exp/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3566d 16h /mod_sim_exp/
58 made fifo full a warning JonasDC 3569d 16h /mod_sim_exp/
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 3569d 16h /mod_sim_exp/
56 this is a branch to test performance of a new style of ram JonasDC 3569d 18h /mod_sim_exp/
55 updated resource usage in comments JonasDC 3570d 15h /mod_sim_exp/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3570d 15h /mod_sim_exp/
53 correctly inferred ram for altera dual port ram JonasDC 3570d 22h /mod_sim_exp/
52 correct inferring of blockram, no additional resources. JonasDC 3570d 22h /mod_sim_exp/
51 true dual port ram for xilinx JonasDC 3570d 23h /mod_sim_exp/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3570d 23h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3582d 18h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 3582d 18h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 3650d 23h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3650d 23h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3650d 23h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3654d 16h /mod_sim_exp/
43 made the core parameters generics JonasDC 3654d 16h /mod_sim_exp/

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