Rev |
Log message |
Author |
Age |
Path |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4086d 19h |
/mod_sim_exp |
62 |
not used anymore |
JonasDC |
4086d 22h |
/mod_sim_exp |
61 |
updated comments, added optional altera constraint |
JonasDC |
4086d 22h |
/mod_sim_exp |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4089d 12h |
/mod_sim_exp |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4089d 13h |
/mod_sim_exp |
58 |
made fifo full a warning |
JonasDC |
4092d 13h |
/mod_sim_exp |
57 |
new fifo design, is now generic (verified with altera and xilinx) and uses block ram |
JonasDC |
4092d 13h |
/mod_sim_exp |
56 |
this is a branch to test performance of a new style of ram |
JonasDC |
4092d 16h |
/mod_sim_exp |
55 |
updated resource usage in comments |
JonasDC |
4093d 12h |
/mod_sim_exp |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4093d 13h |
/mod_sim_exp |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4093d 19h |
/mod_sim_exp |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4093d 20h |
/mod_sim_exp |
51 |
true dual port ram for xilinx |
JonasDC |
4093d 20h |
/mod_sim_exp |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4093d 20h |
/mod_sim_exp |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4105d 15h |
/mod_sim_exp |
48 |
Tag of the starting version of the project |
JonasDC |
4105d 15h |
/mod_sim_exp |
47 |
added documentation for the IP core. |
JonasDC |
4173d 20h |
/mod_sim_exp |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4173d 20h |
/mod_sim_exp |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4173d 20h |
/mod_sim_exp |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4177d 14h |
/mod_sim_exp |
43 |
made the core parameters generics |
JonasDC |
4177d 14h |
/mod_sim_exp |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4183d 22h |
/mod_sim_exp |
41 |
removed deprecated files from version control |
JonasDC |
4183d 22h |
/mod_sim_exp |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4192d 02h |
/mod_sim_exp |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4192d 13h |
/mod_sim_exp |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4192d 18h |
/mod_sim_exp |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4196d 15h |
/mod_sim_exp |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4197d 12h |
/mod_sim_exp |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4197d 14h |
/mod_sim_exp |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4197d 15h |
/mod_sim_exp |