URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 73

Rev	Log message	Author	Age	Path
53	correctly inferred ram for altera dual port ram	JonasDC	4090d 13h	/mod_sim_exp/
52	correct inferring of blockram, no additional resources.	JonasDC	4090d 13h	/mod_sim_exp/
51	true dual port ram for xilinx	JonasDC	4090d 14h	/mod_sim_exp/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4090d 14h	/mod_sim_exp/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4102d 09h	/mod_sim_exp/
48	Tag of the starting version of the project	JonasDC	4102d 09h	/mod_sim_exp/
47	added documentation for the IP core.	JonasDC	4170d 13h	/mod_sim_exp/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4170d 14h	/mod_sim_exp/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4170d 14h	/mod_sim_exp/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4174d 07h	/mod_sim_exp/