URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 77

Rev	Log message	Author	Age	Path
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4092d 06h	/mod_sim_exp
56	this is a branch to test performance of a new style of ram	JonasDC	4092d 09h	/mod_sim_exp
55	updated resource usage in comments	JonasDC	4093d 05h	/mod_sim_exp
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4093d 06h	/mod_sim_exp
53	correctly inferred ram for altera dual port ram	JonasDC	4093d 12h	/mod_sim_exp
52	correct inferring of blockram, no additional resources.	JonasDC	4093d 13h	/mod_sim_exp
51	true dual port ram for xilinx	JonasDC	4093d 13h	/mod_sim_exp
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4093d 13h	/mod_sim_exp
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4105d 08h	/mod_sim_exp
48	Tag of the starting version of the project	JonasDC	4105d 09h	/mod_sim_exp