OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 78

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
78 updated documentation with new RAM style information JonasDC 3479d 07h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 3485d 04h /mod_sim_exp/
76 testbench update JonasDC 3487d 15h /mod_sim_exp/
75 made rw_address a vector of a fixed width JonasDC 3487d 15h /mod_sim_exp/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3490d 11h /mod_sim_exp/
73 updated plb interface, mem_style and device generics added JonasDC 3491d 11h /mod_sim_exp/
72 deleted old resources JonasDC 3492d 11h /mod_sim_exp/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 3492d 11h /mod_sim_exp/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3492d 11h /mod_sim_exp/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3492d 11h /mod_sim_exp/
68 branch no longer needed JonasDC 3492d 13h /mod_sim_exp/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 3492d 14h /mod_sim_exp/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 3492d 14h /mod_sim_exp/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3500d 06h /mod_sim_exp/
64 added synthesis reports of xilinx and altera JonasDC 3500d 11h /mod_sim_exp/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 3500d 11h /mod_sim_exp/
62 not used anymore JonasDC 3500d 14h /mod_sim_exp/
61 updated comments, added optional altera constraint JonasDC 3500d 14h /mod_sim_exp/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3503d 04h /mod_sim_exp/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3503d 05h /mod_sim_exp/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.