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[/] [mod_sim_exp/] - Rev 80

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Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4088d 07h /mod_sim_exp/
79 Tag for version 1.3 (with new ram style JonasDC 4088d 07h /mod_sim_exp/
78 updated documentation with new RAM style information JonasDC 4088d 07h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 4094d 04h /mod_sim_exp/
76 testbench update JonasDC 4096d 15h /mod_sim_exp/
75 made rw_address a vector of a fixed width JonasDC 4096d 15h /mod_sim_exp/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4099d 11h /mod_sim_exp/
73 updated plb interface, mem_style and device generics added JonasDC 4100d 11h /mod_sim_exp/
72 deleted old resources JonasDC 4101d 11h /mod_sim_exp/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4101d 11h /mod_sim_exp/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4101d 11h /mod_sim_exp/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4101d 11h /mod_sim_exp/
68 branch no longer needed JonasDC 4101d 13h /mod_sim_exp/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4101d 14h /mod_sim_exp/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4101d 14h /mod_sim_exp/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4109d 06h /mod_sim_exp/
64 added synthesis reports of xilinx and altera JonasDC 4109d 11h /mod_sim_exp/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4109d 11h /mod_sim_exp/
62 not used anymore JonasDC 4109d 14h /mod_sim_exp/
61 updated comments, added optional altera constraint JonasDC 4109d 14h /mod_sim_exp/

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