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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 84

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4032d 18h	/mod_sim_exp/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4034d 18h	/mod_sim_exp/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4051d 14h	/mod_sim_exp/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4051d 15h	/mod_sim_exp/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4061d 08h	/mod_sim_exp/
79	Tag for version 1.3 (with new ram style	JonasDC	4061d 08h	/mod_sim_exp/
78	updated documentation with new RAM style information	JonasDC	4061d 08h	/mod_sim_exp/
77	found fault in code, now synthesizes normally	JonasDC	4067d 06h	/mod_sim_exp/
76	testbench update	JonasDC	4069d 17h	/mod_sim_exp/
75	made rw_address a vector of a fixed width	JonasDC	4069d 17h	/mod_sim_exp/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4072d 13h	/mod_sim_exp/
73	updated plb interface, mem_style and device generics added	JonasDC	4073d 12h	/mod_sim_exp/
72	deleted old resources	JonasDC	4074d 12h	/mod_sim_exp/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4074d 12h	/mod_sim_exp/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4074d 12h	/mod_sim_exp/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4074d 12h	/mod_sim_exp/
68	branch no longer needed	JonasDC	4074d 15h	/mod_sim_exp/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4074d 15h	/mod_sim_exp/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4074d 16h	/mod_sim_exp/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4082d 08h	/mod_sim_exp/
64	added synthesis reports of xilinx and altera	JonasDC	4082d 13h	/mod_sim_exp/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4082d 13h	/mod_sim_exp/
62	not used anymore	JonasDC	4082d 16h	/mod_sim_exp/
61	updated comments, added optional altera constraint	JonasDC	4082d 16h	/mod_sim_exp/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4085d 06h	/mod_sim_exp/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4085d 07h	/mod_sim_exp/
58	made fifo full a warning	JonasDC	4088d 07h	/mod_sim_exp/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4088d 07h	/mod_sim_exp/
56	this is a branch to test performance of a new style of ram	JonasDC	4088d 09h	/mod_sim_exp/
55	updated resource usage in comments	JonasDC	4089d 06h	/mod_sim_exp/

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[/] [mod_sim_exp/] - Rev 84

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