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[/] [mod_sim_exp/] - Rev 84

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Rev Log message Author Age Path
64 added synthesis reports of xilinx and altera JonasDC 4371d 12h /mod_sim_exp/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4371d 12h /mod_sim_exp/
62 not used anymore JonasDC 4371d 15h /mod_sim_exp/
61 updated comments, added optional altera constraint JonasDC 4371d 15h /mod_sim_exp/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4374d 05h /mod_sim_exp/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4374d 05h /mod_sim_exp/
58 made fifo full a warning JonasDC 4377d 05h /mod_sim_exp/
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4377d 05h /mod_sim_exp/
56 this is a branch to test performance of a new style of ram JonasDC 4377d 08h /mod_sim_exp/
55 updated resource usage in comments JonasDC 4378d 05h /mod_sim_exp/

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