OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 92

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
92 updated documentation with minor interrupt changes of AXI interface JonasDC 3959d 14h /mod_sim_exp/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3961d 17h /mod_sim_exp/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3963d 08h /mod_sim_exp/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4027d 06h /mod_sim_exp/
88 small update on documentation, changed fault in axi control_reg JonasDC 4033d 07h /mod_sim_exp/
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus
JonasDC 4033d 08h /mod_sim_exp/
86 update on previous JonasDC 4033d 08h /mod_sim_exp/
85 changed so that reset now also affects slave register JonasDC 4033d 08h /mod_sim_exp/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4034d 16h /mod_sim_exp/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4036d 17h /mod_sim_exp/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4053d 13h /mod_sim_exp/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4053d 13h /mod_sim_exp/
80 renamed to version 1.1 to follow the versioning system JonasDC 4063d 07h /mod_sim_exp/
79 Tag for version 1.3 (with new ram style JonasDC 4063d 07h /mod_sim_exp/
78 updated documentation with new RAM style information JonasDC 4063d 07h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 4069d 05h /mod_sim_exp/
76 testbench update JonasDC 4071d 16h /mod_sim_exp/
75 made rw_address a vector of a fixed width JonasDC 4071d 16h /mod_sim_exp/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4074d 12h /mod_sim_exp/
73 updated plb interface, mem_style and device generics added JonasDC 4075d 11h /mod_sim_exp/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.