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[/] [mod_sim_exp/] - Rev 93

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Rev Log message Author Age Path
93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 3980d 02h /mod_sim_exp/
92 updated documentation with minor interrupt changes of AXI interface JonasDC 3980d 02h /mod_sim_exp/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3982d 05h /mod_sim_exp/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3983d 19h /mod_sim_exp/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4047d 18h /mod_sim_exp/
88 small update on documentation, changed fault in axi control_reg JonasDC 4053d 19h /mod_sim_exp/
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus
JonasDC 4053d 19h /mod_sim_exp/
86 update on previous JonasDC 4053d 19h /mod_sim_exp/
85 changed so that reset now also affects slave register JonasDC 4053d 19h /mod_sim_exp/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4055d 04h /mod_sim_exp/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4057d 05h /mod_sim_exp/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4074d 01h /mod_sim_exp/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4074d 01h /mod_sim_exp/
80 renamed to version 1.1 to follow the versioning system JonasDC 4083d 19h /mod_sim_exp/
79 Tag for version 1.3 (with new ram style JonasDC 4083d 19h /mod_sim_exp/
78 updated documentation with new RAM style information JonasDC 4083d 19h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 4089d 16h /mod_sim_exp/
76 testbench update JonasDC 4092d 03h /mod_sim_exp/
75 made rw_address a vector of a fixed width JonasDC 4092d 03h /mod_sim_exp/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4094d 23h /mod_sim_exp/

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