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[/] [mod_sim_exp/] - Rev 96

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Rev Log message Author Age Path
96 minor makefile update JonasDC 3493d 08h /mod_sim_exp/
95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
JonasDC 3493d 08h /mod_sim_exp/
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3506d 04h /mod_sim_exp/
93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 3508d 09h /mod_sim_exp/
92 updated documentation with minor interrupt changes of AXI interface JonasDC 3508d 09h /mod_sim_exp/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3510d 12h /mod_sim_exp/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3512d 03h /mod_sim_exp/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3576d 01h /mod_sim_exp/
88 small update on documentation, changed fault in axi control_reg JonasDC 3582d 02h /mod_sim_exp/
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus
JonasDC 3582d 02h /mod_sim_exp/
86 update on previous JonasDC 3582d 02h /mod_sim_exp/
85 changed so that reset now also affects slave register JonasDC 3582d 02h /mod_sim_exp/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3583d 11h /mod_sim_exp/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 3585d 12h /mod_sim_exp/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 3602d 08h /mod_sim_exp/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 3602d 08h /mod_sim_exp/
80 renamed to version 1.1 to follow the versioning system JonasDC 3612d 02h /mod_sim_exp/
79 Tag for version 1.3 (with new ram style JonasDC 3612d 02h /mod_sim_exp/
78 updated documentation with new RAM style information JonasDC 3612d 02h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 3617d 23h /mod_sim_exp/

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