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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0/] - Rev 100

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100 added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated JonasDC 3473d 16h /mod_sim_exp/tags/Release_1.0/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3746d 12h /mod_sim_exp/trunk/
23 added descriptive comments JonasDC 3746d 13h /mod_sim_exp/trunk/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 3749d 07h /mod_sim_exp/trunk/
21 changed x_i signal to xi JonasDC 3750d 15h /mod_sim_exp/trunk/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 3750d 15h /mod_sim_exp/trunk/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 3755d 10h /mod_sim_exp/trunk/
18 updated stages with comments and renamed some signals for consistency JonasDC 3756d 10h /mod_sim_exp/trunk/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 3756d 15h /mod_sim_exp/trunk/
16 package with modified generic parameter for register_n JonasDC 3757d 04h /mod_sim_exp/trunk/
15 changed generic for register width from n to width for consistency JonasDC 3757d 04h /mod_sim_exp/trunk/
14 changed comments, file is now according to OC design rules JonasDC 3757d 04h /mod_sim_exp/trunk/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 3757d 04h /mod_sim_exp/trunk/
12 updated comments, file is now completely according to design rules JonasDC 3757d 04h /mod_sim_exp/trunk/
11 simulation output folder JonasDC 3757d 07h /mod_sim_exp/trunk/
10 changed signal input port names to correct name JonasDC 3757d 09h /mod_sim_exp/trunk/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 3757d 09h /mod_sim_exp/trunk/
8 added descriptive comments JonasDC 3757d 11h /mod_sim_exp/trunk/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3757d 12h /mod_sim_exp/trunk/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3757d 12h /mod_sim_exp/trunk/

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