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[/] [mod_sim_exp/] [tags/] [Release_1.0/] [sim/] [Makefile] - Rev 104

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100 added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated JonasDC 3942d 05h /mod_sim_exp/tags/Release_1.0/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 4215d 02h /mod_sim_exp/tags/Release_1.0/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4226d 17h /mod_sim_exp/tags/Release_1.0/sim/Makefile

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