URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0] - Rev 100

Rev	Log message	Author	Age	Path
5	not needed on svn, is generated by testbench	JonasDC	4215d 08h	/mod_sim_exp/tags/Release_1.0
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4215d 10h	/mod_sim_exp/tags/Release_1.0
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4216d 00h	/mod_sim_exp/tags/Release_1.0
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4220d 05h	/mod_sim_exp/tags/Release_1.0
1	The project and the structure was created	root	4222d 05h	/mod_sim_exp/tags/Release_1.0