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[/] [mod_sim_exp/] [tags/] [Release_1.0] - Rev 100

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5 not needed on svn, is generated by testbench JonasDC 3626d 16h /mod_sim_exp/tags/Release_1.0
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3626d 18h /mod_sim_exp/tags/Release_1.0
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3627d 08h /mod_sim_exp/tags/Release_1.0
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3631d 14h /mod_sim_exp/tags/Release_1.0
1 The project and the structure was created root 3633d 13h /mod_sim_exp/tags/Release_1.0

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