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[/] [mod_sim_exp/] [tags/] [Release_1.1/] - Rev 15

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Rev Log message Author Age Path
15 changed generic for register width from n to width for consistency JonasDC 4237d 05h /mod_sim_exp/tags/Release_1.1/
14 changed comments, file is now according to OC design rules JonasDC 4237d 05h /mod_sim_exp/tags/Release_1.1/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4237d 05h /mod_sim_exp/tags/Release_1.1/
12 updated comments, file is now completely according to design rules JonasDC 4237d 05h /mod_sim_exp/tags/Release_1.1/
11 simulation output folder JonasDC 4237d 08h /mod_sim_exp/tags/Release_1.1/
10 changed signal input port names to correct name JonasDC 4237d 10h /mod_sim_exp/tags/Release_1.1/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4237d 10h /mod_sim_exp/tags/Release_1.1/
8 added descriptive comments JonasDC 4237d 13h /mod_sim_exp/tags/Release_1.1/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4237d 13h /mod_sim_exp/tags/Release_1.1/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4237d 13h /mod_sim_exp/tags/Release_1.1/
5 not needed on svn, is generated by testbench JonasDC 4237d 13h /mod_sim_exp/tags/Release_1.1/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4237d 15h /mod_sim_exp/tags/Release_1.1/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4238d 05h /mod_sim_exp/tags/Release_1.1/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4242d 11h /mod_sim_exp/tags/Release_1.1/
1 The project and the structure was created root 4244d 10h /mod_sim_exp/tags/Release_1.1/

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