| Rev |
Log message |
Author |
Age |
Path |
| 23 |
added descriptive comments |
JonasDC |
4192d 22h |
/mod_sim_exp/tags/Release_1.1/ |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4195d 16h |
/mod_sim_exp/tags/Release_1.1/ |
| 21 |
changed x_i signal to xi |
JonasDC |
4196d 23h |
/mod_sim_exp/tags/Release_1.1/ |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4196d 23h |
/mod_sim_exp/tags/Release_1.1/ |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4201d 18h |
/mod_sim_exp/tags/Release_1.1/ |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4202d 18h |
/mod_sim_exp/tags/Release_1.1/ |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4202d 23h |
/mod_sim_exp/tags/Release_1.1/ |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4203d 12h |
/mod_sim_exp/tags/Release_1.1/ |
| 15 |
changed generic for register width from n to width for consistency |
JonasDC |
4203d 12h |
/mod_sim_exp/tags/Release_1.1/ |
| 14 |
changed comments, file is now according to OC design rules |
JonasDC |
4203d 13h |
/mod_sim_exp/tags/Release_1.1/ |
| 13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4203d 13h |
/mod_sim_exp/tags/Release_1.1/ |
| 12 |
updated comments, file is now completely according to design rules |
JonasDC |
4203d 13h |
/mod_sim_exp/tags/Release_1.1/ |
| 11 |
simulation output folder |
JonasDC |
4203d 15h |
/mod_sim_exp/tags/Release_1.1/ |
| 10 |
changed signal input port names to correct name |
JonasDC |
4203d 18h |
/mod_sim_exp/tags/Release_1.1/ |
| 9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4203d 18h |
/mod_sim_exp/tags/Release_1.1/ |
| 8 |
added descriptive comments |
JonasDC |
4203d 20h |
/mod_sim_exp/tags/Release_1.1/ |
| 7 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4203d 20h |
/mod_sim_exp/tags/Release_1.1/ |
| 6 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4203d 21h |
/mod_sim_exp/tags/Release_1.1/ |
| 5 |
not needed on svn, is generated by testbench |
JonasDC |
4203d 21h |
/mod_sim_exp/tags/Release_1.1/ |
| 4 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4203d 22h |
/mod_sim_exp/tags/Release_1.1/ |
