URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] - Rev 87

Rev	Log message	Author	Age	Path
29	added software for generation of test input for the tesbenches	JonasDC	4197d 03h	/mod_sim_exp/tags/Release_1.1
28	updated makefile for new pipeline sources	JonasDC	4197d 04h	/mod_sim_exp/tags/Release_1.1
27	test input values for multiplier_tb	JonasDC	4197d 04h	/mod_sim_exp/tags/Release_1.1
26	testbench for only the montgommery multiplier	JonasDC	4197d 04h	/mod_sim_exp/tags/Release_1.1
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4197d 04h	/mod_sim_exp/tags/Release_1.1
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4200d 13h	/mod_sim_exp/tags/Release_1.1
23	added descriptive comments	JonasDC	4200d 14h	/mod_sim_exp/tags/Release_1.1
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4203d 07h	/mod_sim_exp/tags/Release_1.1
21	changed x_i signal to xi	JonasDC	4204d 15h	/mod_sim_exp/tags/Release_1.1
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4204d 15h	/mod_sim_exp/tags/Release_1.1