URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [bench/] [vhdl/] - Rev 93

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4077d 07h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4117d 07h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4185d 12h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
43	made the core parameters generics	JonasDC	4189d 05h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4208d 07h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
26	testbench for only the montgommery multiplier	JonasDC	4210d 06h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4213d 15h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4225d 07h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4229d 13h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/