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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 80

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Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4069d 11h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4109d 11h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4177d 16h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
43 made the core parameters generics JonasDC 4181d 10h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4200d 11h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4205d 19h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4217d 11h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4221d 17h /mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd

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