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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] - Rev 93

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80 renamed to version 1.1 to follow the versioning system JonasDC 4133d 01h /mod_sim_exp/tags/Release_1.1/rtl/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4173d 01h /mod_sim_exp/tags/Release_0.1.0/rtl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4241d 06h /mod_sim_exp/trunk/rtl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4245d 00h /mod_sim_exp/trunk/rtl/
43 made the core parameters generics JonasDC 4245d 00h /mod_sim_exp/trunk/rtl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4251d 07h /mod_sim_exp/trunk/rtl/
41 removed deprecated files from version control JonasDC 4251d 07h /mod_sim_exp/trunk/rtl/
40 adjusted core instantiation to new core module name JonasDC 4259d 11h /mod_sim_exp/trunk/rtl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4259d 23h /mod_sim_exp/trunk/rtl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4260d 04h /mod_sim_exp/trunk/rtl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4264d 01h /mod_sim_exp/trunk/rtl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4264d 21h /mod_sim_exp/trunk/rtl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4265d 01h /mod_sim_exp/trunk/rtl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4265d 04h /mod_sim_exp/trunk/rtl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4265d 05h /mod_sim_exp/trunk/rtl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4265d 10h /mod_sim_exp/trunk/rtl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4265d 10h /mod_sim_exp/trunk/rtl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4266d 00h /mod_sim_exp/trunk/rtl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4269d 09h /mod_sim_exp/trunk/rtl/
23 added descriptive comments JonasDC 4269d 10h /mod_sim_exp/trunk/rtl/

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