OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] - Rev 98

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4076d 09h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4116d 10h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4184d 15h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4188d 08h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
43 made the core parameters generics JonasDC 4188d 08h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4194d 16h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4194d 16h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4202d 20h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4203d 07h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4203d 13h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4207d 10h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4208d 06h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4208d 10h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4208d 12h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4208d 13h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4208d 19h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4208d 19h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4209d 09h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4212d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
23 added descriptive comments JonasDC 4212d 19h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.