URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] - Rev 86

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4077d 06h	/mod_sim_exp/tags/Release_1.1/sim/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4117d 06h	/mod_sim_exp/tags/Release_0.1.0/sim/
41	removed deprecated files from version control	JonasDC	4195d 12h	/mod_sim_exp/trunk/sim/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4209d 05h	/mod_sim_exp/trunk/sim/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4209d 15h	/mod_sim_exp/trunk/sim/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4209d 15h	/mod_sim_exp/trunk/sim/
28	updated makefile for new pipeline sources	JonasDC	4210d 05h	/mod_sim_exp/trunk/sim/
27	test input values for multiplier_tb	JonasDC	4210d 05h	/mod_sim_exp/trunk/sim/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4213d 14h	/mod_sim_exp/trunk/sim/
11	simulation output folder	JonasDC	4224d 09h	/mod_sim_exp/trunk/sim/
5	not needed on svn, is generated by testbench	JonasDC	4224d 14h	/mod_sim_exp/trunk/sim/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4225d 06h	/mod_sim_exp/trunk/sim/