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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] - Rev 93

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80 renamed to version 1.1 to follow the versioning system JonasDC 4133d 00h /mod_sim_exp/tags/Release_1.1/sim/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4173d 01h /mod_sim_exp/tags/Release_0.1.0/sim/
41 removed deprecated files from version control JonasDC 4251d 07h /mod_sim_exp/trunk/sim/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4264d 23h /mod_sim_exp/trunk/sim/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4265d 09h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4265d 10h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 4266d 00h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 4266d 00h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4269d 09h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 4280d 03h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 4280d 09h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4281d 00h /mod_sim_exp/trunk/sim/

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