URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] [Makefile] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4065d 22h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4105d 22h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
41	removed deprecated files from version control	JonasDC	4184d 04h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4198d 07h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4198d 07h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
28	updated makefile for new pipeline sources	JonasDC	4198d 21h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4202d 06h	/mod_sim_exp/tags/Release_1.1/sim/Makefile
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4213d 22h	/mod_sim_exp/tags/Release_1.1/sim/Makefile